The present invention relates to VLSI circuit testing techniques. Specifically, a linear feedback shift register for inclusion on a VLSI integrated circuit is described which is programmable for carrying out several common test functions.
The complexity of very large scale integrated circuits, VLSI, renders the testing of such circuits very difficult and expensive. To alleviate the difficulty, circuit testability has been designed into the VLSI circuit. In the past, as outlined in a paper reported in the IEEE Journal of Solid State Circuits, Vol. SC-15, No. June 3, 1980, entitled "Built-In Test for Complex Digital Integrated Circuits", a built-in register provides for an input signal drive for circuits under test, and a test answer evaluator in the form of another register permits evaluation of the result of applying the input signal drive to the circuit under test.
The built-in registers have been used as a scan generator to apply a test pattern to the device and compare the circuit response to the test patterns with the applied test patterns. The register may be operated in a serial shift register linear (LSR) mode, permitting the desired test pattern to be serially entered into the register and then latched to provide a desired parallel input to a circuit under test. The circuit under test is then rendered operable and the response to the input is parallel loaded in another LSR mode register. The response to the test is then serially read out to determine whether the circuit under test functioned appropriately. These techniques are generically referred to as level sensitive scan design, LSSD.
More sophisticated testing is performed through the use of random pattern generation and corresponding signature analysis operating the LSR as a linear feedback shift register. The random pattern is generated by a linear differential shift register with appropriate feedback to generate a polynomial pseudo-random number. The polynomial is applied to the circuit under test. The response of the circuit under test to the continuously changing random number is "hashed" or compressed by another linear differential shift register operated as a signature analyzer to preserve any detected errors. At the end of the pattern generation sequence, the hashed result is serially read from the signature analyzer to determine whether the circuit under test performed appropriately.
The on-chip testing techniques using SRL registers all produce hardware overhead for the chip. Additionally, the linear feedback shift register requires feedback connections and control lines adding to the device pin out.